1. Field of the Invention
This invention relates generally to microprocessors and, more particularly, to a microprocessor capable of automatically performing multiple bus cycles.
2. Description of the Prior Art
In general, microprocessors initiate a data transfer operation during an address phase of a bus cycle by providing via an address bus an access address to which a particular piece of peripheral equipment is uniquely responsive. The actual data exchange is thereafter performed during a data transfer phase of the bus cycle. Typically, the microprocessor must execute one or more additional instructions if more data must be exchanged. Thus, for example, if the microprocessor is capable of operating internally on say 16 bit operands but the data bus is only 8 bits wide, then each time a 16 bit operand must be exchanged with the memory equipment the microprocessor must execute the instructions necessary to perform two 8 bit transfer operations. Even in microprogrammed microprocessors which have substantially autonomous bus control logic, additional microinstructions are required to set up the internal routing of the second 8 bits, increment the access address to the next address, and instruct the bus control logic to perform the second bus cycle using the new address.